With the development of display technology, people's demand on image quality is increasing, and flat panel display devices with high quality and high resolution are becoming more and more popular, and have been paid more and more attention by display panel manufacturers.
Thin film transistors (TFTs) are main driving devices in a flat display panel, which directly affect the development direction of high performance flat panel display devices. A thin film transistor may be of various structures, and there are various materials for manufacturing the thin film transistors of corresponding structures, for example, amorphous silicon and polysilicon are commonly used in the manufacture of thin film transistors. However, amorphous silicon itself has many inherent shortcomings such as low mobility and low stability, and in contrast, low temperature polysilicon (LTPS) has high stability and mobility which may be, for example, up to tens or even hundreds of times of that of amorphous silicon. Therefore, the technique in which the thin film transistor is made of low temperature polysilicon has been developed rapidly, and new generation liquid crystal display (LCD) devices or organic light-emitting diode (OLED) display devices derived from LTPS have become an important display technology, especially the OLED display devices have been acclaimed by users for their characteristics such as ultra-thinness, low power consumption and self-emission.
FIG. 1 is a sectional diagram of a structure of a LTPS TFT array substrate in the prior art. The array substrate comprises a buffer layer 2, an active layer 3, a first insulation layer 4′, a gate 5, a second insulation layer 6′, a source 71, a drain 72, a third insulation layer 8′, a planarization layer 9 and a pixel electrode 10 sequentially provided on a base 1. At present, the array substrate of this structure may be manufactured by eight patterning processes using eight masks, wherein the eight patterning processes include:
forming a pattern including the active layer 3 through a first patterning process by using an active layer mask (a-Si Mask);
performing a partial p-Si doping on the first insulation layer 4′ to form a pattern including a first plate 11 of a storage capacitor Cs through a second patterning process by using a storage capacitor mask (Cs mask). In this step, the first plate 11 of the storage capacitor Cs is formed by doping through a first ion implantation, however, the storage capacitor Cs in which the first plate 11 formed by using the ion implantation has a disadvantage of slow charging and discharging;
forming a pattern including a gate 5 and a second plate 12 of the storage capacitor Cs through a third patterning process by using a gate mask. In this step, a gate metal is used as the second plate 12 of the storage capacitor Cs;
forming a pattern including contact holes connecting the source 71 and the drain 72 with the active layer 3 in the second insulation layer 6′ through a fourth patterning process by using a contact mask;
forming a pattern including the source 71 and the drain 72 through a fifth patterning process by using a source/drain mask (S/D mask);
forming a pattern including a bridge via hole between the pixel electrode 10 and the drain 72 in the third insulation layer 8′ through a sixth patterning process by using a via hole mask;
forming a pattern including a bridge via hole between the pixel electrode 10 and the drain 72 in the planarization layer 9 through a seventh patterning process by using a planarization mask (PLN mask), and making the array substrate be planarized so as to deposit a electrode layer on the planarized substrate; and
forming a pattern including the pixel electrode 10 through an eighth patterning process by using a pixel electrode mask (ITO mask).
It can be seen that the existing manufacturing process for the array substrate including the LTPS and Cs is complicate and has relatively more procedures, resulting in a high production cost.